Liquid crystal display device

ABSTRACT

A liquid crystal display device having a narrowed peripheral area, particularly, a liquid crystal display device in which disconnection or short-circuiting of connecting lines disposed in the peripheral area is restrained is provided. The liquid crystal display device includes a pixel area having pixel electrodes, and a peripheral area surrounding the pixel area. Gate lines and drain lines are disposed in the pixel area, and a gate driver and a drain driver are disposed in the peripheral area. A plurality of gate connecting lines which connect the gate driver and a plurality of gate lines are stacked in the peripheral area.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a liquid crystal display device,and more particularly, to a liquid crystal display device having anenlarged image display area.

[0002] Liquid crystal display devices are used in television sets,personal computers, and displays for mobile terminals.

[0003] An active matrix type of liquid crystal display device hastransparent substrates disposed in opposition to each other with aliquid crystal interposed therebetween.

[0004]FIG. 20 is a diagram of interconnection lines provided on and atthe periphery of a transparent substrate of a related-art liquid crystaldisplay device which is being manufactured.

[0005] A liquid-crystal-side surface of one of transparent substrates isprovided with gate lines GW disposed to be extended in the x (lateral)direction and to be juxtaposed in the y (longitudinal) direction, anddrain (source) lines DW disposed to be extended in the y direction andto be juxtaposed in the x direction.

[0006] The gate lines GW and the drain lines DW cross one another atright angles, and a switching element and a pixel electrode are formedin each area surrounded by adjacent ones of the gate lines GW andadjacent ones of the drain lines DW, thereby forming a so-called pixel.The switching element is turned on by a scanning signal supplied fromthe corresponding one of the gate lines GW, and the pixel electrode issupplied with a video signal from the corresponding one of the drainlines DW via the switching element. The areas surrounded by the gatelines GW and the drain lines DW constitute a pixel area AR.

[0007] Mobile terminals are being reduced more and more in body size,whereas their image display areas are being enlarged more and more torealize better visibility of information. For this reason, in the shownliquid crystal display device, the proportion of the pixel area AR inthe transparent substrate is increasing more and more, whereas aperipheral area surrounding the pixel area AR is decreasing more andmore. In the liquid crystal display device, circuit chips for drivingits liquid crystal (hereinafter referred to as drivers) and connectinglines are disposed in the peripheral area.

[0008] The gate lines GW and the drain lines DW are electricallyconnected to a gate driver and a drain driver via gate connecting linesGC and drain connecting lines DC, respectively. In the liquid crystaldisplay device, if its display area is made larger, the distance betweeneach of the gate connecting lines GC or the drain connecting lines DCbecomes shorter because of its narrow peripheral area, resulting in theproblem of electrical shorting of the gate connecting lines GC or thedrain connecting lines DC. In addition, if each of the gate connectinglines GC or the drain connecting lines DC is made thin, the problem ofdisconnection occurs.

[0009] Furthermore, as the peripheral area becomes narrower, an area inwhich the drivers are disposed becomes smaller.

[0010] A gate driver GDr has gate signal output terminals on a long sidecloser to the pixel area AR. The gate connecting lines GC pass through aportion under the gate driver GDr and are connected to a gate commonline GCOM. Accordingly, terminals for transmitting or receiving signalscannot be disposed on the side of the gate driver GDr that is closer toa short side of a panel PNL.

SUMMARY OF THE INVENTION

[0011] A liquid crystal display device according to the inventionincludes transparent substrates disposed in opposition to each otherwith a liquid crystal interposed therebetween. One of the transparentsubstrates is provided with a plurality of gate lines disposed to beextended in the x (lateral) direction and to be juxtaposed in the y(longitudinal) direction, and a plurality of drain (source) linesdisposed to be extended in the y direction and to be juxtaposed in the xdirection. This substrate has a peripheral area which surrounds a pixelarea formed the plurality of gate lines and the plurality of drainlines.

[0012] The plurality of gate lines are connected to a plurality of gateconnecting lines formed in the peripheral area. The plurality of gateconnecting lines are stacked in the peripheral area.

[0013] The gate connecting lines extend to a gate common line on a sidedifferent from a side where a driver is disposed.

[0014] Drain connecting lines are disposed under a gate driver.

[0015] According to this construction, it is possible to provide aliquid crystal display device having a reduced peripheral area.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016]FIG. 1 is a plan view of a substrate of a liquid crystal displaydevice according to the invention;

[0017]FIG. 2 is a layout diagram of drain connecting lines according tothe invention;

[0018]FIG. 3 is a cross-sectional view taken along line I-I of FIG. 1;

[0019]FIG. 4 is a cross-sectional view taken along line II-II of FIG. 1;

[0020]FIG. 5 is a cross-sectional view showing another example of theconstruction of the gate connecting lines according to the invention;

[0021]FIG. 6 is a plan view of a substrate of a liquid crystal displaydevice having another structure according to the invention;

[0022]FIG. 7 is a cross-sectional view taken along line III-III of FIG.6;

[0023]FIG. 8 is a plan view of a liquid crystal display device unitwhich drives two liquid crystal display devices by means of one driveraccording to the invention;

[0024]FIG. 9 is a cross-sectional view of a substrate of a liquidcrystal display device according to the invention, and a cross-sectionalview taken along line IV-IV of FIG. 8;

[0025]FIG. 10 is a plan view of a substrate of a liquid crystal displaydevice according to a second embodiment of the invention;

[0026]FIG. 11 is a cross-sectional view taken along line V-V of FIG. 10;

[0027]FIG. 12 is a cross-sectional view taken along line VI-VI of FIG.10;

[0028]FIG. 13 is a plan view of interconnection lines provided on and atthe periphery of the substrate of the liquid crystal display deviceaccording to the invention;

[0029]FIG. 14 is a plan view of interconnection lines provided on and atthe periphery of the substrate of the liquid crystal display deviceaccording to the invention;

[0030]FIG. 15 is a plan view of a substrate of a liquid crystal displaydevice having another construction according to the invention;

[0031]FIG. 16 is a schematic enlarged view of the liquid crystal displaydevice of the invention in which a driver is disposed;

[0032]FIG. 17 is a schematic enlarged view of the liquid crystal displaydevice of the invention in which the driver DR is disposed;

[0033]FIG. 18 is a top plan perspective view of the gate driver shown inFIG. 17;

[0034]FIG. 19 is a plan view showing the layout of the drain connectinglines DC; and

[0035]FIG. 20 is a diagram of interconnection lines provided on and atthe periphery of a transparent substrate of a related-art liquid crystaldisplay device which is being manufactured.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0036] A first embodiment of the invention will be described below withreference to the accompanying drawings.

[0037] In each of the following embodiments, parts and portions havingthe same functions are denoted by the same reference numerals.

[0038]FIG. 1 is a plan view of a substrate of a liquid crystal displaydevice according to the invention. FIG. 1 is a plan view of a liquidcrystal display device for a mobile terminal, which has an effectivescreen with a diagonal size of about 5.08 cm, and is also a plan view ofa transparent substrate on which pixel electrodes are formed. The liquidcrystal display device shown in FIG. 1 adopts an active matrix scheme.

[0039] The active matrix type of liquid crystal display device isprovided with polygonal substrates disposed in opposition to each other,and has a liquid crystal layer between the first substrate and thesecond substrate.

[0040] Common electrodes are formed on the second substrate. Each of thecommon electrodes and the corresponding one of the pixel electrodes forma capacitor to hold a voltage.

[0041] A liquid-crystal-side surface of the first substrate PNL1 isprovided with gate lines GW disposed to be extended in the x (lateral)direction and to be juxtaposed in the y (longitudinal) direction, anddrain lines (or source lines) DW insulated from the gate lines GW anddisposed to be extended in the y direction and to be juxtaposed in the xdirection.

[0042] In each area which is surrounded by mutually adjacent ones of thegate lines GW and mutually adjacent ones of the drain lines DW, aswitching element and a pixel electrode are formed to constitute aso-called pixel. The switching element is turned on by a scanning signalsupplied from the corresponding one of the gate lines GW, while thepixel electrode is supplied with a video signal from the correspondingone of the drain lines DW via the switching element. One example of theswitching element is a thin film transistor.

[0043] A gate driver GDr and a drain driver DDr are mounted on a panelPNL along one short side thereof by a flip chip attachment scheme. Thegate driver GDr is connected to the gate lines GW, while the draindriver DDr is connected to the drain lines DW.

[0044]FIG. 1 shows part of the plurality of gate lines GW. In FIG. 1,there are shown a gate line GW1 for controlling the most distant pixelsfrom the gate driver GDr, a gate line GW2 adjacent to the gate line GW1,a gate line GW4 for controlling the central pixels of the screen of thepanel PNL, a gate line GW3 adjacent to the gate line GW4 and positionedon a more distant side from gate driver GDr, a gate line GW5 adjacent tothe gate line GW4 and positioned on a side closer to the gate driverGDr, a gate line GW6 adjacent to the gate line GW5, a gate line GWm forcontrolling the closest pixels to the gate driver GDr, and a gate lineGWm-1 adjacent to the gate line GWm. The gate lines GW1, GW2, GW3, GW4,GW5, GW6, GWm-1 and GWm are respectively electrically connected to gateconnecting lines GC1, GC2, GC3, GC4, GC5, GC6, GCm-1 and GCm. The gateconnecting lines GC1, GC2, GC3, GC4, GC5, GC6, GCm-1 and GCm areconnected to the gate driver GDr.

[0045]FIG. 1 shows part of the plurality of drain lines DW. In FIG. 1,there are shown drain lines DW1 and DWn which are respectively disposedon lateral opposite ends of a pixel area AR. The area surrounded by thegate line GW1 and GWm and the drain lines DW1 and DWn is the pixel areaAR. No pixels are formed in a peripheral area AP of the panel PNL.

[0046] The panel PNL shown in FIG. 1 is a rectangular substrate havingshort sides and long sides.

[0047] In the peripheral area AP, the gate connecting lines GC and acommon line VCL are disposed in an area GA1 along one of the long sides(hereinafter referred to as the first long side area GA1).Charge-holding lines SW and a common line VCL are disposed in an areaGA2 along the other of the long sides (hereinafter referred to as thesecond long side area GA2) in the peripheral area AP. The common linesVCL are electrically connected to the common electrodes disposed inopposition to the first substrate PNL1 via a common line connectingterminal VCP.

[0048] In the peripheral area AP, IC chips for driving the liquidcrystal display device are fixed in an area DA1 along one of the shortsides (hereinafter referred to as the first short side area DA1).

[0049] The driver circuit chip DDr electrically connected to the drainlines DW (hereinafter referred to the drain driver) DDr) is disposed inan area containing the central portion of the first short side area DA1.The drain lines DW and the drain driver DDr are interconnected by drainconnecting lines DC.

[0050]FIG. 2 is a layout diagram of the drain connecting lines DC in theperipheral area AP on the side where the drain driver DDr is disposed.

[0051] A first drain connecting line DC1 positioned on the leftmost sideand a second drain connecting line DC2 adjacent to the first drainconnecting line DC1 are spaced apart from each other by a distance DP.

[0052] Since the first drain connecting line DC1 and the second drainconnecting line DC2 are disposed in parallel with each other, thedistance DP can be made constant, and the width of each of the drainconnecting lines DC can be made constant. Accordingly, electricalshort-circuiting and disconnection can be restrained from occurring inany of the drain connecting lines DC over the entire length thereof.

[0053] The interconnection resistances of the respective drainconnecting lines DC are made uniform from a drain connecting lineextending to the most distant position from the drain driver DDr to adrain connecting line extending to the closest position. Since theinterconnection resistances are uniform, the rounding of signalwaveforms supplied from the drain driver DDr to individual pixels isuniformized. Since the interconnection resistances are uniformized,variations in display characteristic among the pixels can be reduced.

[0054] As the difference in length between each of the drain connectinglines DC is made smaller and the distance DP is made larger, theinterconnection resistances of the respective drain connecting lines DCcan be uniformized more easily. The distance DP can be calculated byDP=sin θ1×P, where P is a pixel pitch. The pixel pitch P is a value tobe determined according to the type of product, and the distance DP canbe increased by increasing the angle θ1.

[0055] Since the drain driver DDr is disposed in the central portion ofthe first short side area DA1, the distance DP can be maximized.

[0056] The driver circuit chip (hereinafter referred to the gate driver)GDr which is electrically connected to the gate lines GW is disposed onthe left side of the drain driver DDr with a space interposedtherebetween. According to this construction, the drain driver DDr needsonly to be mounted on one side of the first substrate PNL1, and theperipheral area AP of the first substrate PNL1 can be made small on theother side on which no drivers are disposed.

[0057] The gate driver GDr is of a rectangular shape having long sidesparallel to the short sides of the panel PNL and short sides parallel tothe long sides of the panel PNL. The gate connecting lines GC areconnected to terminals provided on the long and short sides of the gatedriver GDr that are exposed to the display area AR.

[0058] Since part of the terminals are provided on the short side of thegate driver GDr, the long sides of the gate driver GDr can be madeshort, whereby an increase in the peripheral area AP can be restrained.In addition, since the long sides of the gate driver GDr can be madeshort, the incident angle θ1 of the drain connecting lines DC withrespect to the Y axis can be increased, whereby the yield factor ofmanufacture can be improved.

[0059] The gate connecting lines GC1, GC2, GC3 and GC4 are connected tothe upper half (more distant from the gate driver GDr) of the gateconnecting lines GC of the pixel area AR, while the gate connectinglines GC5, GC6, GCm-1 and GCm are connected to the lower half (closer tothe gate driver GDr) of the gate connecting lines GC of the pixel areaAR, and each of the gate connecting lines GC1, GC2, GC3 and GC4 isdisposed to overlap a respective one of the gate connecting lines GC5,GC6, GCm-1 and GCm. In a first long side area GA1, the gate connectingline GC1 and the gate connecting line GC5 overlap each other, the gateconnecting line GC2 and the gate connecting line GC6 overlap each other,the gate connecting line GC3 and the gate connecting line GCm-1 overlapeach other, and the gate connecting line GC4 and the gate connectingline GCm overlap each other.

[0060] In the first short side area DA1, the gate connecting line GC5 isinsulated from and crosses the gate connecting lines GC1, GC2, GC3 andGC4 which are connected to the upper half of the gate connecting linesGC.

[0061]FIG. 3 is a cross-sectional view taken along line I-I of FIG. 1.

[0062] The gate connecting lines GC1, GC2, GC3 and GC4 are connected tothe upper half (more distant from the gate driver GDr) of the gateconnecting lines GC of the pixel area AR are respectively disposed tooverlie the gate connecting lines GC5, GC6, GCm-1 and GCm connected tothe lower half (closer to the gate driver GDr) of the gate connectinglines GC of the pixel area AR.

[0063] As shown in FIG. 3, the underlying gate connecting lines GC5,GC6, GCm-1 and GCm are formed on the panel PNL, and the overlying gateconnecting lines GC1, GC2, GC3 and GC4 are respectively formed tooverlie the underlying gate connecting lines GC5, GC6, GCm-1 and GCm.The gate connecting lines GC3 and GC4 are overlying gate lines whichextend to climb over the underlying gate connecting lines GCm-1 and GCm,respectively.

[0064] The overlying gate connecting lines GC1, GC2, GC3 and GC4 and theunderlying gate connecting lines GC5, GC6, GCm-1 and GCm are controlledin different manners.

[0065] Each of the underlying gate connecting lines GC5, GC6, GCm-1 andGCm is has an oxide film 1 formed by being oxidized on its surface. Afirst protective film 2 for the purpose of electrical insulation betweenthe underlying gate connecting lines GC5, GC6, GCm-1 and GCm and theoverlying gate connecting lines GC1, GC2, GC3 and GC4 is formed on thefirst protective film 2. A second protective film 4 is formed on theoverlying gate overlying gate connecting lines GC1, GC2, GC3 and GC4.The protection of the gate connecting lines GC and the insulationthereof from other interconnection lines can be realized by the secondprotective film 4.

[0066] The pixel area AR of the panel PNL has the first gate line GW1and the second gate line GW2, and the first gate connecting line GC1which electrically connects the gate line GW1 to the liquid crystaldriving circuit GDr and the second gate connecting line GC2 whichelectrically connects the gate line GW2 to the liquid crystal drivingcircuit GDr are disposed in the peripheral area AP. The first gateconnecting line GC1 and the second gate connecting line GC2 are stackedin the thickness direction of the panel PNL, whereby the pixel area ARcan be made narrow and the pixel area AR can be made large.

[0067] In addition, the width of each of the gate connecting lines GCcan be made thick, whereby the disconnection of any of the gateconnecting lines GC can be restrained. Furthermore, the distance betweeneach of the gate lines GW can be made long, whereby the short-circuitingbetween the gate lines GW can be restrained.

[0068]FIG. 4 is a cross-sectional view taken along line I-I of FIG. 1.

[0069] The gate connecting line GC3 is formed on an amorphous siliconlayer 3 formed on the first protective film 2. The gate connecting lineGC3 overlaps part of the gate line GW3, and is electrically connected tothe gate line GW3.

[0070] The gate line GW3 has an oxide film 1 on its surface, but doesnot have an oxide film in the portion of the gate line GW3 that isconnected to the gate connecting line GC3. In this construction, thegate line GW3 and the gate connecting line GC3 are electricallyconnected to each other.

[0071]FIG. 5 is a cross-sectional view showing another example of theconstruction of the gate connecting lines GC, and is a cross-sectionalview showing another example of the construction of the cross sectiontaken along line I-I of FIG. 1. In FIG. 5, the overlying gate connectinglines GC1 to GC4 and the underlying gate connecting lines GC5 to GCm aredisposed to be shifted from one another.

[0072] As shown in FIG. 5, any of the overlying gate connecting linesGC1 to GC4 is formed between each of the underlying gate connectinglines GC5 to GCm, whereby it is possible to reduce an added capacitancewhich is applied between each of the overlying gate connecting lines GC1to GC4 and a respective one of the underlying gate connecting lines GC5to GCm. Accordingly, it is possible to reduce the influence of waveformrounding and noise on image quality.

[0073]FIG. 6 is a plan view of the substrate of a liquid crystal displaydevice having another structure according to the invention.

[0074] The gate connecting lines GC shown in FIG. 6 are arranged so thattwo adjacent gate connecting lines connected to each pair of gate linesadjacent to each other are disposed in a vertically stacked manner.According to this structure, it is possible to reduce the number ofcrossings of the gate connecting lines GC near the gate driver GDr.

[0075]FIG. 7 is a cross-sectional view taken along line III-III of FIG.6.

[0076] The gate connecting line GC1 adjacent to the gate connecting lineGC2 is disposed over the gate connecting line GC2.

[0077] The underlying gate connecting line GC2 has the oxide film 1 onits surface, and the top surface of the oxide film 1 is covered with thefirst protective film 2. The amorphous silicon layer 3 is formed on thefirst protective film 2. The underlying gate connecting lines GC and theoverlying gate connecting lines GC are positively insulated from eachother by the first protective film 2 and the amorphous silicon layer 3.

[0078]FIG. 8 is a plan view of substrates of a liquid crystal displaydevice unit in which two separate liquid crystal display devices aredriven by one drain driver.

[0079] The liquid crystal display device unit has a construction inwhich one gate driver and one drain driver drive two liquid crystaldisplay devices, i.e., the first liquid crystal display device and thesecond liquid crystal display device. The first liquid crystal displaydevice and the second liquid crystal display device have a first pixelarea AR1 and a second pixel area AR2, respectively.

[0080] The first liquid crystal display device has a liquid crystallayer between a first substrate PNL1 and a second substrate PNL2, andthe second liquid crystal display device has a liquid crystal layerbetween a third substrate PNL3 and a fourth substrate PNL4. Elementssuch as gate lines, drain lines, gate connecting lines, drain connectinglines, switching elements and pixel electrodes are formed on the firstsubstrate PNL1 and the third substrate PNL3 of the substrates PNL1 toPNL4.

[0081] The gate driver GDr and the drain driver DDr are disposed in thefirst short side area DA1 of the first substrate PNL1.Flexible-printed-circuit-board connecting pads FPAD for connection to aflexible printed circuit board FPC are formed in an area DA2 of theperipheral area of the first substrate PNL1 on the other short sidethereof (hereinafter referred to as the second short side area DA2).

[0082] One end of the flexible printed circuit board FPC is connected tothe flexible-printed-circuit-board connecting pads FPAD of the firstsubstrate PNL1, while the other end of the flexible printed circuitboard FPC is connected to the flexible-printed-circuit-board connectingpads FPAD of the third substrate PNL3.

[0083] Gate connecting lines GMC and the drain connecting lines DC areconnected to the flexible-printed-circuit-board connecting pads FPAD ofthe first substrate PNL1. The gate connecting lines GMC and the drainconnecting lines DC are respectively connected to the gate lines and thedrain lines of the third substrate PNL3 via the flexible printed circuitboard FPC.

[0084] The gate connecting lines GMC for the second liquid crystaldisplay device are connected to the gate driver GDr by an arbitrarynumber of lines (k lines). The gate connecting lines GMC for the secondliquid crystal display device are disposed to overlie the gateconnecting lines GC so that the arbitrary number of the gate connectinglines GMC are juxtaposed in ascending order from the first gateconnecting line GC1 connected to the most distant gate line GW1 from thegate driver GDr. According to this construction, the number of crossingsof the gate connecting lines GMC for the second liquid crystal displaydevice and the gate lines GW is decreased, whereby the disconnection ofthe gate lines GW can be prevented.

[0085] The gate connecting lines GMC1 and GMCk for the second liquidcrystal display device are respectively connected to gate lines GMW1 andGMk of the third substrate PNL3 via the flexible printed circuit boardFPC.

[0086]FIG. 9 is a cross-sectional view of the first substrate PNL1, andis a cross-sectional view taken along line IV-IV of FIG. 8.

[0087] The gate connecting line GMC1 connected to the gate line GMW1formed on the third substrate PNL3 is disposed to overlie the first gateconnecting line GC1 connected to the gate line GW1 formed on the firstsubstrate PNL1.

[0088] The gate connecting line GMCk connected to the gate line GMWkformed on the third substrate PNL3 is disposed to overlie the first gateconnecting line GCk connected to the gate line GWk formed on the firstsubstrate PNL1.

[0089] Each of the gate connecting lines GC has the oxide film 1 on itssurface, and the oxide film 1 is covered with the first protective film2. The amorphous silicon layer 3 is formed on the first protective film2. The underlying gate connecting lines GC and the overlying gateconnecting lines GMC are positively insulated from each other by thefirst protective film 2 and the amorphous silicon layer 3.

[0090] A second embodiment of the invention will be described below.

[0091]FIG. 10 is a plan view of a glass plate GL including a substrateof a liquid crystal display device according to the second embodiment ofthe invention.

[0092] The panel PNL is cut from the glass plate GL on which thin filmtransistors and peripheral interconnection lines are formed.

[0093] The gate lines GW are connected to a gate common line GCOMdisposed outside the panel PNL. Voltage is supplied from the gate commonline GCOM to form the oxide film 1 on the surface of each of the gatelines GW (anodic oxidation).

[0094] In order to enable static electricity to escape during amanufacturing process, the drain lines DW extends to the second shortside area DA2 opposed to the first short side area DA1 in which thedrain driver DDr is disposed, and is electrically connected to a draincommon line DCOM beyond a short side of the panel PNL.

[0095] The charge-holding lines SW are electrically connected to thegate common line GCOM disposed outside the panel PNL. The charge-holdinglines SW extend to the gate common line GCOM from the same side as thegate lines GW. Voltage is supplied from the gate common line GCOM tooxidize the surface of each of the gate lines GW.

[0096] The gate lines GW and the charge-holding lines SW are disposedparallel to one another, and the common line VCL is disposed to crossthe gate lines GW and the charge-holding lines SW at right angles.

[0097]FIG. 11 is a cross-sectional view taken along line V-V of FIG. 10.The gate lines GW4 and GW5 and charge-holding lines SW4 and SW5 areformed on the panel PNL. The gate lines GW4 and GW5 and thecharge-holding lines SW4 and SW5 are formed of aluminum. The surfacelayer of aluminum is oxidized. In addition, the protective film 4 isformed to cover the gate lines GW4 and GW5 and the charge-holding linesSW4 and SW5. The protective film 4 is formed to protect the lines GW4,GW5, SW4 and SW5 and to insulate the lines GW4, GW5, SW4 and SW5 fromone another.

[0098]FIG. 12 is a cross-sectional view taken along line VI-VI of FIG.10. The gate lines GW (GW4 and GW5) and the charge-holding lines SW (SW4and SW5) are formed on the substrate PNL. The gate lines GW4 and GW5 andthe charge-holding lines SW4 and SW5 are formed of aluminum.

[0099] Each of the gate lines GW (GW4 and GW5) has an oxidized surfacelayer. The first protective film 2 is stacked on the gate lines GW (GW4and GW5) each having the oxidized surface layer. The amorphous siliconlayer 3 is stacked on the first protective film 2.

[0100] The charge-holding lines SW (SW4 and SW5) are formed at the samelevel as the gate lines GW (GW4 and GW5), and an oxide layer does notoverlie the portion of any of the charge-holding lines SW (SW4 and SW5)that is connected to the common line VCL. During anodic oxidation, theportion of each of the charge-holding lines SW (SW4 and SW5) that isconnected to the common line VCL is covered with a resist so that theoxidation of the connection portion is prevented.

[0101] Holes are formed in the first protective film 2 and the amorphoussilicon layer 3 formed on the charge-holding lines SW (SW4 and SW5).

[0102] The common line VCL is formed on the amorphous silicon layer 3.Since the first protective film 2 and the amorphous silicon layer 3overlie the gate lines GW (GW4 and GW5), the gate lines GW (GW4 and GW5)are insulated from the common line VCL. The holes are formed in thefirst protective film 2 and the amorphous silicon layer 3 formed on thecharge-holding lines SW (SW4 and SW5), thereby providing electricalconnection between the common line VCL and the charge-holding lines SW(SW4 and SW5).

[0103] The second protective film 4 is formed on the common line VCL inorder to protect the common line VCL and insulate the common line VCLfrom other lines.

[0104] In the structure shown in FIG. 12, the gate lines GW (GW4 andGW5) and the charge-holding lines SW (SW4 and SW5) are electricallyconnected to the gate common line GCOM for anodic oxidation, whereby anoxide layer can be formed on each of the gate lines GW (GW4 and GW5) andthe charge-holding lines SW (SW4 and SW5) and the charge-holding linesSW (SW4 and SW5) can be connected to the common line VCL.

[0105] When the glass plate GL is cut along the external shape of thepanel PNL, the gate lines GW are divided into individual gate lines.

[0106] Since the gate lines GW and the charge-holding lines SW connectedto the gate common line GCOM for anodic oxidation are disposed on thesame side as the common line VCL, lines which have heretofore beendisposed under the gate driver GDr and connected to the gate common lineGCOM in the related art become unnecessary.

[0107]FIG. 13 is a plan view of interconnection lines provided on and atthe periphery of the panel PNL of the liquid crystal display device.

[0108] A cross-sectional structure of the circled area T shown in FIG.13 is constructed as shown in FIG. 12.

[0109] The common line VCL extend in parallel with the gate lines GW.

[0110] In the liquid crystal display device shown in FIG. 13, the gatelines GW and the charge-holding lines SW are connected to the gatecommon line GCOM in the second short side area DA2 opposite to the firstshort side area DA1 in which the gate driver GDr is disposed.

[0111] In addition, in the liquid crystal display device shown in FIG.13, the drain lines DW connected to the drain common line DCOM and thegate lines GW and the charge-holding lines SW connected to the gatecommon line GCOM are disposed on only one side, troubles due to staticelectricity can be reduced. Specifically, it is possible to reducetroubles such as the trouble of static electricity which is charged tocause variations in the thresholds of individual TFTs and causenon-uniformity in display. In addition, it is possible to reducedisconnection due to electrolytic corrosion.

[0112] The gate lines GW and the charge-holding lines SW connected tothe gate common line GCOM are disposed to extend toward the gate commonline GCOM on a side except the side where the gate driver GDr ismounted.

[0113] According to the second embodiment, since the gate lines GW andthe charge-holding lines SW connected to the gate common line GCOM aredisposed on the side except the side where the gate driver GDr ismounted, lines which have heretofore been disposed under the gate driverGDr and connected to the gate common line GCOM become unnecessary.Accordingly, the gate driver GDr can have terminals disposed on allsides, and can be reduced in size.

[0114] Each of the charge-holding lines SW has the oxide film in thedisplay area AR. This is because since the charge-holding lines SW crossthe drain lines DW at right angles similarly to the gate lines GWcrossing the drain lines DW at right angles, the charge-holding lines SWneed to have the same structure as the gate lines GW. Short-circuitingof the charge-holding lines SW can be restrained by the oxide filmformed as an insulating layer.

[0115] The common line VCL has the role of feeding a common voltage tothe common electrodes and the role of applying a constant voltage to thecharge-holding lines SW. If the resistance of the common line VCL withrespect to the charge-holding lines SW greatly differs between the topand the bottom of the screen of the panel PNL, a voltage drop willoccur, resulting in luminance irregularity. Accordingly, the common lineVCL is made thick to reduce the difference in the resistance of thecommon line VCL with respect to the charge-holding lines SW between thetop and the bottom of the screen.

[0116]FIG. 14 is a plan view of interconnection lines provided on and atthe periphery of the panel PNL of the liquid crystal display device.

[0117] A cross-sectional structure of each of the circled areas T and Ushown in FIG. 14 is constructed as shown in FIG. 12.

[0118] The gate lines GW and the charge-holding lines SW connected tothe gate common line GCOM are disposed to extend to the gate common lineGCOM in the first short side area DA1 where the gate driver GDr ismounted, and in the second short side area DA2. In the liquid crystaldisplay device shown in FIG. 14, the half of the lines GW and SWconnected to the gate common line GCOM, which half are closer to thegate driver GDr, extend to the gate common line GCOM in the first shortside area DA1 where the gate driver GDr is mounted. On the other hand,the half of the lines GW and SW connected to the gate common line GCOM,which half are more distant from the gate driver GDr, extend to the gatecommon line GCOM in the second short side area DA2.

[0119] According to the structure shown in FIG. 14, the second long sidearea GA2 can be made narrow.

[0120]FIG. 15 is a plan view of the layout of interconnection lines inthe case where the gate driver GDr and the drain driver DDr are formedon one chip. FIG. 15 shows interconnection lines inside the panel PNL aswell as interconnection lines outside the panel PNL which are beingmanufactured.

[0121] The gate connecting lines GC are connected to the right and leftsides of a driver Dr.

[0122] The half of the gate lines GW that are more distant from thedriver Dr extend in parallel with the gate lines GW and are connected tothe gate common line GCOM, i.e., pass through the first long side areaGA1 and are connected to the gate common line GCOM.

[0123] The gate connecting lines GC connected to the half of the gatelines GW that are closer to the driver Dr extend into a portion underthe driver Dr and are connected to the gate common line GCOM.

[0124] According to the structure shown in FIG. 15, the number ofinterconnection lines passing through the portion under the driver Drcan be reduced.

[0125] A third embodiment of the invention will be described below.

[0126]FIG. 16 is a schematic enlarged view of part of theinterconnection lines of the panel PNL in which the driver Dr isdisposed.

[0127] The gate driver GDr and the drain driver DDr are mounted on thepanel PNL by a flip chip attachment scheme.

[0128] Drain connecting lines DC1 a and DC2 a are respectively connectedto terminals disposed on the short side of the drain driver DDr that iscloser to the gate driver GDr. The drain connecting line DC1 a isconnected to the terminal disposed at the closest position to the shortside of the panel PNL, while the drain connecting line DC2 a isconnected to the terminal disposed at the closest position to the pixelarea AR. These drain connecting lines DC1 a and DC2 a are disposed toavoid the gate driver GDr.

[0129] The drain connecting line DC1 a has an angle O₂ with respect tothe pixel area AR in the vicinity of the pixel area AR. Namely, thedrain connecting line DC1 a has the angle O₂ with respect to a lineparallel to the gate lines GW in the vicinity of the pixel area AR. Inaddition, the drain connecting line DC1 a has an angle θ3 with a lineparallel to the gate lines GW in the vicinity of the drain driver DDr.

[0130] The drain connecting line DC3 a is connected to a terminal whichis disposed at the closest position to the gate driver GDr, of all theterminals provided on a long side of the drain driver DDr. The drainconnecting line DC3 a has an angle θ4 with respect to the line parallelto the gate lines GW.

[0131] The relationship between the angle O₂ and the angle θ3 is θ2<θ3.

[0132] According to this construction, the peripheral area AP can bemade narrow.

[0133]FIG. 17 is a schematic enlarged view of part of theinterconnection lines of the panel PNL in which the driver Dr isdisposed.

[0134] The drain connecting lines DC which are respectively electricallyconnected to terminals disposed on the short side of the drain driverDDr that is closer to the gate driver GDr pass through a portion underthe gate driver GDr and are electrically connected to the drain linesDW.

[0135] Drain connecting lines DC1 b and DC2 b are respectively connectedto the terminals disposed on the short side of the drain driver DDr thatis closer to the gate driver GDr. The drain connecting line DC1 b isconnected to the terminal disposed at the closest position to the shortside of the panel PNL, while the drain connecting line DC2 b isconnected to the terminal disposed at the closest position to the pixelarea AR.

[0136] In FIG. 17, the drain connecting line DC1 b has an angle θ5 withrespect to a line parallel to the gate lines GW in the vicinity of thepixel area AR. The drain connecting lines DC1 b and DC2 b connected tothe short side of the drain driver DDr that is closer to the gate driverGDr are disposed to be partly parallel to the gate lines GW.

[0137] These drain connecting lines DC1 b and DC2 b pass through aportion under the gate driver GDr.

[0138] The drain connecting line DC3 b is connected to a terminal whichis disposed at the closest position to the gate driver GDr, of all theterminals provided on a long side of the drain driver DDr. The drainconnecting line DC3 b has an angle θ6 with respect to the line parallelto the gate lines GW.

[0139] These drain connecting lines DC1 b and DC2 b pass through theportion under the gate driver GDr. Accordingly, the angle θ5 betweeneach of the drain connecting lines DC1 b and DC2 b and the pixel area ARcan be increased. Therefore, the distance between each adjacent one ofthe drain connecting lines DC can be made large, whereby theshort-circuiting between the drain lines DW can be reduced.

[0140] The angle θ5 shown in FIG. 17 can be made larger than the angleθ4 shown in FIG. 16.

[0141] According to this construction, the peripheral area AP can bemade narrow, and the short-circuiting between the drain lines DW can berestrained. In addition, the disconnection of the drain lines DW can berestrained.

[0142] The third embodiment may also be applied to a liquid crystaldisplay device of the type in which the gate driver GDr and the draindriver DDr are mounted on the panel PNL as two independent driversaccording to the other embodiments.

[0143]FIG. 18 is a top plan perspective view of the gate driver GDrshown in FIG. 17, and is a view showing the layout of terminals.

[0144] The gate driver GDr is rectangular, and terminals 8 are providedon each of the sides of the gate driver GDr. A first output terminalgroup GOUT1 is disposed on one of the short sides of the gate driverGDr, while a second area 6 through which the drain connecting lines DCcan pass and a gate signal terminal group G2 are disposed on the othershort side. The short side where the second area 6 and the gate signalterminal group G2 are disposed is the short side closer to the draindriver DDr.

[0145] A second output terminal group GOUT2 and a first area 5 throughwhich the drain connecting lines DC can pass are disposed on one of thelong sides of the gate driver GDr, particularly on the long side closerto the pixel area AR. A third area 7 through which to pass lines foranodic oxidation of the gate lines GW and an input/output terminal groupG1 of the gate driver GDr are disposed on the other long side of thegate driver GDr.

[0146] The terminals 8 provided in the first area 5 and the second area6 are dummy terminals, and the drain lines DW may also be disposed underthe first area 5 and the second area 6 so that the electricalinterference between the internal circuit of the gate driver GDr and thedrain lines DW can be prevented.

[0147] According to the above-described construction, it is possible toreduce the peripheral area AP surrounding the pixel area AR.

[0148]FIG. 19 is a view showing the construction of the thirdembodiment, and is a plan view showing the layout of the drainconnecting lines DC.

[0149] Part of the drain connecting lines DC electrically connected tothe short side of the drain driver DDr that is closer to the gate driverGDr pass through a portion under the gate driver GDr and areelectrically connected to the drain lines DW.

[0150] Two of the drain connecting lines DC shown in FIG. 19, i.e., adrain connecting line DC1 c positioned on the outermost side and a drainconnecting lines DC2 c adjacent to the drain connecting line DC1 c, passthrough a portion between dummy terminals and are connected to the drainlines DW.

[0151] According to the above-described construction, it is possible toreduce the peripheral area AP of the panel PNL that surrounds the pixelarea AR.

What is claimed is:
 1. A liquid crystal display device comprising aliquid crystal layer between a first substrate and a second substrate,the first substrate including a pixel area having pixel electrodes, anda peripheral area surrounding the pixel area, the pixel area includinggate lines and drain lines, the gate lines including first gate linesand second gate lines, first gate connecting lines and second gateconnecting lines being disposed in the peripheral area, the respectivefirst gate connecting lines electrically connecting the first gate linesto a liquid crystal driving circuit, the respective second gate lineselectrically connecting the second gate lines to the liquid crystaldriving circuit, the first gate connecting lines and the second gateconnecting lines being stacked in a thickness direction of the firstsubstrate.
 2. A liquid crystal display device according to claim 1,wherein the first gate lines are more distant from the liquid crystaldriving circuit than are the second gate lines, and the first gateconnecting lines are positioned at a higher level than are the secondgate connecting lines.
 3. A liquid crystal display device according toclaim 1, wherein the pixel area is divided into two areas.
 4. A liquidcrystal display device comprising: a first substrate and a secondsubstrate disposed in opposition to each other; and a liquid crystallayer interposed between the first substrate and the second substrate,the first substrate including gate lines extending in a lateraldirection, drain lines extending in a longitudinal direction, pixelelectrodes, and charge-holding capacitance lines extending in parallelwith the gate lines, capacitors being formed between the pixelelectrodes and common electrodes disposed in opposition to the pixelelectrodes, the common electrodes being electrically connected to thecharge-holding lines via a common line, the gate lines being disposedunder the common line in an insulated state.
 5. A liquid crystal displaydevice according to claim 4, wherein the common line extends in parallelwith the drain lines.
 6. A liquid crystal display device comprising aliquid crystal layer between a first substrate and a second substrate,the first substrate including gate lines and drain lines in a pixelarea, a gate driver and a drain driver being provided in a peripheralarea surrounding the pixel area, the gate lines being electricallyconnected to the gate driver by gate connecting lines, the drain linesbeing electrically connected to the drain driver by drain connectinglines, the drain connecting lines passing through a portion under thegate driver and electrically connecting the drain lines to the draindriver.
 7. A liquid crystal display device according to claim 6, whereinthe drain driver has a rectangular shape with short sides and longsides, the drain connecting lines being electrically connected to ashort side of the drain driver.